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74LVX3245 8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
July 1993 Revised September 2003
74LVX3245 8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
General Description
The LVX3245 is a dual-supply, 8-bit translating transceiver that is designed to interface between a 3V bus and a 5V bus in a mixed 3V/5V supply environment. The Transmit/ Receive (T/R) input determines the direction of data flow. Transmit (active-HIGH) enables data from A Ports to B Ports; Receive (active-LOW) enables data from B Ports to A Ports. The Output Enable input, when HIGH, disables both A and B Ports by placing them in a high impedance condition. The A Port interfaces with the 3V bus; the B Port interfaces with the 5V bus. The LVX3245 is suitable for mixed voltage applications such as notebook computers using 3.3V CPU and 5V peripheral components.
Features
s Bidirectional interface between 3V and 5V buses s Inputs compatible with TTL level s 3V data flow at A Port and 5V data flow at B Port s Outputs source/sink 24 mA s Guaranteed simultaneous switching noise level and dynamic threshold performance s Implements proprietary EMI reduction circuitry s Functionally compatible with the 74 series 245
Ordering Code:
Order Number 74LVX3245WM 74LVX3245QSC 74LVX3245MTC Package Number M24B MQA24 MTC24 Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names OE T/R A0-A7 B0-B7 Description Output Enable Input Transmit/Receive Input Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs
(c) 2003 Fairchild Semiconductor Corporation
DS011620
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74LVX3245
Truth Table
Inputs OE L L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Outputs T/R L H X Bus B Data to Bus A Bus A Data to Bus B HIGH-Z State
Logic Diagram
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74LVX3245
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCCA, VCCB) DC Input Voltage (VI) @ OE, T/R DC Input/Output Voltage (VI/O) @ An @ Bn DC Input Diode Current (IIN) @ OE, T/R DC Output Diode Current (IOK) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) and Max Current @ ICCA @ ICCB Storage Temperature Range (TSTG) DC Latch-Up Source or Sink Current
-0.5V to +7.0V -0.5V to VCCA + 0.5V -0.5V to VCCA + 0.5V -0.5V to VCCB + 0.5V 20 mA 50 mA 50 mA 50 mA 100 mA 200 mA -65C to +150C 300 mA
Recommended Operating Conditions (Note 2)
Supply Voltage VCCA VCCB Input Voltage (VI) @ OE, T/R Input/Output Voltage (VI/O) @ An @ Bn Free Air Operating Temperature (TA) Minimum Input Edge Rate (t/V) VIN from 30% to 70% of VCC VCC @ 3.0V, 4.5V, 5.5V
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: Unused Pins (inputs and I/Os) must be held HIGH or LOW. They may not float.
2.7V to 3.6V 4.5V to 5.5V 0V to VCCA 0V to VCCA 0V to VCCB
-40C to +85C
8 ns/V
DC Electrical Characteristics
Symbol VIHA VIHB Parameter Minimum HIGH Level Input Voltage An, T/R, OE Bn VCCA (V) 3.6 2.7 3.3 3.3 VILA VILB VOHA Minimum HIGH Level Output Voltage Maximum LOW Level Input Voltage An, T/R, OE Bn 3.6 2.7 3.3 3.3 3.0 3.0 2.7 2.7 VOHB VOLA Maximum LOW Level Output Voltage 3.0 3.0 3.0 3.0 2.7 2.7 VOLB IIN Maximum Input Leakage Current @ OE, T/R IOZA Maximum 3-STATE Output Leakage @ An IOZB Maximum 3-STATE Output Leakage @ Bn 3.6 5.5 0.5 5.0 A 3.6 5.5 0.5 5.0 A VI = VIL, VIH OE = VCCA VO = VCCA, GND VI = VIL, VIH OE = VCCA VO = VCCB, GND 3.6 5.5 0.1 1.0 A VI = VCCB, GND 3.0 3.0 VCCB (V) 5.0 5.0 4.5 5.5 5.0 5.0 4.5 5.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 2.99 2.65 2.5 2.3 4.5 4.25 0.002 0.21 0.11 0.22 0.002 0.18 TA = +25C Typ 2.0 2.0 2.0 2.0 0.8 0.8 0.8 0.8 2.9 2.35 2.3 2.1 4.4 3.86 0.1 0.36 0.36 0.42 0.1 0.36 TA = -40C to +85C Guaranteed Limits 2.0 2.0 2.0 2.0 0.8 0.8 0.8 0.8 2.9 2.25 2.2 2.0 4.4 3.76 0.1 0.44 0.44 0.5 0.1 0.44 V V V V IOUT = -100 A IOH = -24 mA IOH = -12 mA IOH = -24 mA IOUT = -100 A IOH = -24 mA IOUT =100 A IOL = 24 mA IOL = 12 mA IOL = 24 mA IOUT = 100 A IOL = 24 mA V VOUT 0.1V or VCC -0.1V V VOUT 0.1V or VCC - 0.1V Units Conditions
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74LVX3245
DC Electrical Characteristics
Symbol ICC Maximum ICCT/Input @ ICCA Quiescent VCCA Supply Current ICCB Quiescent VCCB Supply Current VOLPA VOLPB VOLVA VOLVB VIHDA VIHDB VILDA VILDB Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage 3.6 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.6 Parameter Bn An, T/R, OE VCCA (V) 3.6 3.6
(Continued)
VCCB (V) 5.5 5.5 TA = +25C Typ 1.0 1.35 0.35 TA = -40C to +85C Guaranteed Limits 1.5 0.5 mA mA VI = VCCB - 2.1V VI = VCCA -0.6V An = VCCA or GND 5.5 5 50 A Bn = VCCB or GND, OE = GND, T/R = GND An = VCCA or GND 5.5 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 8 0.8 1.5 -0.8 -1.2 2.0 2.0 0.8 0.8 80 A Bn = VCCB or GND, OE = GND, T/R = VCCA V V V V (Note 3) (Note 4) (Note 3) (Note 4) (Note 3) (Note 5) (Note 3) (Note 5)
Units
Conditions
Note 3: Worst case package. Note 4: Max number of outputs defined as (n). Data inputs are driven 0V to VCC level; one output at GND. Note 5: Max number of Data Inputs (n) switching. (n-1) inputs switching 0V to VCC level. Input-under-test switching: VCC level to threshold (VIHD), 0V to threshold (VILD), f = 1 MHz.
AC Electrical Characteristics
TA = +25C CL = 50 pF Symbol Parameters VCCA = 3.3V (Note 6) VCCB = 5.0V (Note 7) Min tPHL tPLH tPHL tPLH tPZL tPZH tPZL tPZH tPHZ tPLZ tPHZ tPLZ tOSHL tOSLH Propagation Delay A to B Propagation Delay B to A Output Enable Time OE to B Output Enable Time OE to A Output Disable Time OE to B Output Disable Time OE to A Output to Output Skew (Note 8) Data to Output
Note 6: Voltage Range 3.3V is 3.3V 0.3V. Note 7: Voltage Range 5.0V is 5.0V 0.5V. Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
TA = -40C to +85C CL = 50 pF VCCA = 3.3V (Note 6) VCCB = 5.0V (Note 7) Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 8.5 8.0 8.0 8.0 8.5 9.0 9.0 9.5 8.0 7.5 8.5 7.0 1.5
TA = -40C to +85C CL = 50 pF VCCA = 2.7V VCCB = 5.0V (Note 7) Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 9.0 8.5 8.5 8.5 9.0 9.5 9.5 10.0 8.5 8.0 9.0 7.5 1.5 ns ns ns ns ns ns Units
Typ 5.4 5.6 5.1 5.7 4.8 6.3 6.3 6.8 5.3 4.2 5.3 3.7 1.0
Max 8.0 7.5 7.5 7.5 8.0 8.5 8.5 9.0 7.5 7.0 8.0 6.5 1.5
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0
ns
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74LVX3245
Capacitance
Symbol CIN CI/O CPD Input Capacitance Input/Output Capacitance Power Dissipation Capacitance (Note 9)
Note 9: CPD is measured at 10 MHz
Parameter
Typ 4.5 15 AB BA 55 40
Units pF pF pF VCC = Open VCCA = 3.3V VCCB = 5.0V VCCB = 5.0V VCCA = 3.3V
Conditions
8-Bit Dual Supply Translating Transceiver
The LVX3245 is a dual supply device capable of bidirectional signal translation. This level shifting ability provides an efficient interface between low voltage CPU local bus with memory and a standard bus defined by 5V I/O levels. The device control inputs can be controlled by either the low voltage CPU and core logic or a bus arbitrator with 5V I/O levels. Manufactured on a sub-micron CMOS process, the LVX3245 is ideal for mixed voltage applications such as notebook computers using 3.3V CPU's and 5V peripheral devices.
Power Up Considerations
To insure that the system does not experience unnecessary ICC current draw, bus contention, or oscillations during power up, the following guidelines should be adhered to (refer to Table 1): * Power up the control side of the device first. This is the VCCA. * OE should ramp with or ahead of VCCA. This will help guard against bus contention. * The Transmit/Receive control pin (T/R) should ramp with VCCA, this will ensure that the A Port data pins are configured as inputs. With VCCA receiving power first, the A I/O Port should be configured as inputs to help guard against bus contention and oscillations. * A side data inputs should be driven to a valid logic level. This will prevent excessive current draw. The above steps will ensure that no bus contention or oscillations, and therefore no excessive current draw occurs during the power up cycling of these devices. These steps will help prevent possible damage to the translator devices and potential damage to other system components.
TABLE 1. Low Voltage Translator Power Up Sequencing Table
Device Type 74LVX3245 VCCA 3V (power up 1st) VCCB 5V configurable T/R ramp with VCCA OE ramp with VCCA A Side I/O logic 0V or VCCA B Side I/O outputs Floatable Pin Allowed No
Please reference Application Note AN-5001 for more detailed information on using Fairchild's LVX Low Voltage Dual Supply CMOS Translating Transceivers.
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74LVX3245
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Package Number MQA24
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74LVX3245 8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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